lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
A minimal GPU design in Verilog to learn how GPUs work from the ground up
AXI X-Bar
A simple parametrizable doorbell based mailbox
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Pipelines the AXI path with FIFOs
AMBA AXI VIP
SystemVerilog modules and classes commonly used for verification
RISC-V Debug Support for our PULP RISC-V Cores
Simple single-port AXI memory interface
[UNRELEASED] FP div/sqrt unit for transprecision
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.